1. Field of the Invention
This invention relates to a delay circuit for delaying analog signals, and more particularly to a delay circuit of this kind, which can be suitably integrated into integrated circuits.
2. Prior Art
Conventional delay circuits which are integrated into large scale integrated circuits (hereinafter referred to as "LSIs") include a type that is comprised of a plurality of memory cells formed of switches and capacitors and connected in parallel to each other, and operates such that the voltage of an analog signal is stored sequentially in the memory cells, and upon the lapse of a predetermined time period, the analog signal thus stored is read from the memory cells, to thereby delay the analog signal.
FIG. 1 shows the construction of the conventional delay circuit. In the figure, symbols M1 to Mn designate n memory cells connected in parallel to each other, for storing the voltage of an analog signal. The memory cell M1 is comprised of an input switch SW1, a capacitor C1, and an output switch SW1'. The other memory cells M2 to Mn are similarly constructed. Connected to outputs of the memory cells M1 to Mn is a voltage follower formed of an operational amplifier OP. In the figure, symbol Cp represents parasitic capacitance present at the output side of the memory cells M1 to Mn.
With the above construction, in writing an input analog signal Vin, the input switches Sw1 to Swn are sequentially turned on in the order of SW1.fwdarw.SW2.fwdarw. . . . SWn.fwdarw.SW1 . . . to sample and hold the input analog signal Vin every sampling period so as to store the voltage of the input analog signal in the capacitors C1 to Cn. On the other hand, in reading out the input analog signal Vin thus stored, the output switches SW1' to SWn' are sequentially turned on in the order of SW1'.fwdarw.SW2'.fwdarw. . . . SWn'.fwdarw.SW1' . . . to read out the stored input analog signal Vin sequentially from the memory cells M1 to Mn.
More specifically, the input analog signal Vin is sequentially written into the memory cells M1 to Mn-1, and then, at the next sampling timing the input analog signal Vin is written into the memory cell Mn and at the same time the input analog signal Vin stored in the memory cell M1 is read out, i.e. at delayed timing, to be output from the operational amplifier OP as an output analog signal Vout. In this way, the memory cells M1 to Mn repeatedly carry out writing operation and reading operation in a cyclic manner. Provided that the sampling time period (a time period during which each switch is on) is represented by Ts, the delay time Td can be expressed as Td=(n-1).times.Ts.
In forming a delay circuit having the above described construction within an LSI, the following problem arises: That is, the capacitors C1 to Cn each have a capacitance value of several PFs so that they have high impedance even in a low-frequency region. Consequently, when the delay circuit undergoes disturbance or noise of low frequency (e.g. hum synchronous with the commercial alternating current), the voltage value of the capacitors C1 to Cn changes so that the input analog signal Vin read from the memory cells Ml to Mn has the noise of low frequency superimposed thereupon. If the frequency of the noise component is higher than the frequency band of the signal component, the noise component can be removed from the output analog signal Vout by the use of a low-pass filter. The low-frequency noise like hum, however, has a frequency falling within the frequency band of the output analog signal Vout and hence cannot be removed from the output analog signal Vout with ease. Therefore, even if a delay circuit having the above described construction is integrated into an LSI, the signal-to-noise ratio (SN) is degraded.
Further, the above-described delay circuit also has the disadvantage that the voltage stored in the capacitors C1 to Cn of the memory cells M1 to Mn cannot be accurately read out due to the presence of the parasitic capacitance Cp.
For example, when the switch SW1' is turned off after the voltage is read out from the capacitor C1 of the memory cell M1 with the switch SW1' being on, voltage across the parasitic capacitance Cp corresponds to the voltage which has been stored in the capacitor C1. In this state, voltage Vs" across the capacitor C2 of the next memory cell M2 which is actually read out from the capacitor C2 is given by the following formula: EQU Vs"=(CaVs+CbVs')/(Ca+Cb)
where Vs' represents the voltage across the parasitic capacitance Cp, Cb the capacitance value of the parasitic capacitance Cp, Ca the capacitance value of the capacitor C2, and Vs the voltage across the capacitor C2 before the reading.
It will noted from the above formula that the intrinsic voltage Vs that is to be read out from the capacitor C2 changes to the voltage Vs" due to the action of the parasitic capacitance Cp. Besides, the capacitance value Cb of the parasitic capacitance Cp is dependent upon the voltage, and therefore the parasitic capacitance Cp also constitutes a factor for distortion of the output analog signal Vout.